We’ve covered devices with pins all around and in the middle, but the density train doesn’t end with that technology. The entire bottom of modern chips are connected to the PCB with a grid of pins that have no leads at all. Instead, spheres of solder are attached to the bottom of the device in a grid pattern–these are called ball grid array (BGA) packages. Ball grid array packages have quickly become the most popular packaging choices used in microelectronics.
The earliest BGA packages came with ball-to-ball pitches of 1.27 millimeters; half the spacing of traditional components. A typical via could be used to fan-out and route these packages. To decrease the size of the BGA, the pins were crowded together down to one millimeter pitch. Next came 0.8 mm and then 0.65 mm, which is the finest pitch that can be supported with normal PTH technology boards.
Since high-reliability PCBs (categorized as Class 3 by the IPC) require a larger capture pad for the vias, the party ends with 0.8 mm pitch BGA packages for those applications. For a long time, BGA packages were not considered reliable enough for such applications. They have since found their way into the automotive industry, but mainly to the extent they support through-hole vias. As silicon areas shrink, from 0.5 mm, 0.4 mm down to 0.35 mm, the edge rates of circuits go up and the signal integrity challenges escalate.
When observing a PCB, you might notice traces running between the pads of the BGA. As the ball-pitch decreases, those channels are lost. The area for the fan-out via is also lost. The fine pitch BGA footprints use microvias inside the SMD pads. The further into the middle of the BGA package you go, the deeper into the board you have to go to find a more suitable routing channel. And as a result, stacking is used for the microvias.
Connectors in Through-Hole Technologies
Connectors have some staying power in through-hole technology because of the stress they endure as they are engaged and disengaged. Even so, there is a trend towards using alignment pins along with hybrid solutions that mix through-hole and surface mount pads in the same connector. A great example of this architecture is USB type-C.
When you encounter components like the USB-C connector, there are often some very specific dimensions on the data sheet. Non-plated holes may have very tight tolerances, which can be captured in the pad-stack. There also may be a slot in the board for a mid-mount connector with a unilateral tolerance.
Soldermask, paste stencil apertures, and local fiducial marks are critical to PCB assembly.
This information is important to capture and preserve so it goes into the process of creating the fabrication drawing. A vendor needs to know where to be precise with milling and drilling operations. As a result, some connectors require hard gold or a generous area to engage the mating connector. And the data can be lost if it is not actively managed in the footprints
Small logic circuits, and Axial leaded resistors and capacitors will probably remain popular because they serve an ecosystem for the hobbyist and the low-tech development types of printed circuit boards. Meanwhile, the processors and other advanced chips have left this space behind.
This space has been left behind for more advanced chips due to the size of the vias used for the old-school boards not supporting requirements of the latest generation of devices. One-by-one, the plated through hole components of yesteryear are becoming obsolete. Anyone wishing to make a career out of PCB design is going to have to catch up and keep up with the latest technologies available in microelectronics.
High Density Interconnect (HDI) in Microelectronics
Junior PCB designers are going to have to be versed in micro-vias due to the advancements in microelectronics. Implementing micro-vias in a design comes with a few dependencies. The first concern is that the small diameter of the microvia is difficult to plate unless the hole is shallow. Even a one-to-one ratio of depth to diameter is a challenge.
The typical PCB factory can manage a 100 micron diameter hole size if the thickness of the dielectric is 65 microns or less.
So, the layers have to be quite thin. When a thin layer is used, the geometry of a controlled impedance transmission line also decreases. In order to achieve the thin linewidth, the fabricator has to start with a thinner copper foil. For a top-layer trace, it makes more sense to move the reference plane from layer-2 down to layer-3 and create a void on layer-2 below the run of the transmission line.
Rather than making a void in the layer-2 copper, it is advisable to use a route-keep-out shape so the area remains free of inadvertent routing or copper flood if the shape has to be replaced. This will happen globally when the board outline is revised. Failsafe practices include the use of keep-outs for components and routing as necessary. Design intent will survive future editing even if it is someone else doing the project. That will include capturing design constraints that cover minimum line width and air-gap as well as any length requirements.
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