PCB signal integrity issues mainly include signal reflection, crosstalk, signal delay, and timing errors.
1. Reflection: When the signal is transmitted on the transmission line, when the characteristic impedance of the transmission line on the high-speed PCB does not match the source impedance or load impedance of the signal, the signal will be reflected, causing the signal waveform to overshoot, undershoot and the ringing phenomenon caused by it. Overshoot refers to the first peak (or bottom) of the signal transition. It is an additional voltage effect above the power supply level or below the reference ground level. Undershoot refers to the signal jump change to the next valley (or peak). Excessive overshoot voltage often impacts the device for a long period of time, causing damage to the device. Undershoot will reduce the noise margin. Ringing increases the time required for signal stabilization, which affects system timing.
2. Crosstalk: In PCB, crosstalk refers to the undesired noise interference caused by the electromagnetic energy through the mutual capacitance and mutual inductance coupling to the adjacent transmission line when the signal propagates on the transmission line. It is caused by interaction of different structures of the electromagnetic field in the same area. Mutual capacitance causes coupling current, which is called capacitive crosstalk; while mutual inductance causes coupling voltage, which is called inductive crosstalk. On the PCB, crosstalk is related to trace length, signal line spacing, and the condition of the reference ground plane.
3. Signal delay and timing error: The signal is transmitted at a limited speed on the wires of the PCB, and the signal is sent from the driver to the receiver, with a transmission delay in between. Excessive signal delays or mismatched signal delays can lead to timing errors and disrupted logic device functionality.
High-speed digital system design analysis based on signal integrity analysis can not only effectively improve product performance, but also shorten product development cycles and reduce development costs. With the development of digital systems toward high speed and high density, it is extremely urgent and necessary to master this design weapon. With the continuous improvement and improvement of signal integrity analysis models and calculation analysis algorithms, digital system design methods that use signal integrity for computer design and analysis will be widely and comprehensively applied.
What is the process of PCB signal integrity?
1. Preparations before design
Before the design begins, you must first think and determine the design strategy so that you can guide tasks such as component selection, process selection, and cost control of circuit board production. As far as SI is concerned, it is necessary to carry out investigations in advance to form planning or design guidelines, so as to ensure that the design results do not show obvious SI problems, crosstalk or timing problems.
2. Stack-up of circuit boards
Some project teams have great autonomy in determining the number of PCB layers, while others do not have this autonomy, so it is important to know where you are.
Other important questions include: What is the expected manufacturing tolerance? What is the expected insulation constant on the board? What is the allowable error of line width and spacing? What is the allowable error in the thickness and spacing of the ground and signal layers? All this information can be used during the pre-wiring phase.
Based on the above data, you can choose stack-up. Note that almost every PCB inserted into another circuit board or backplane has a thickness requirement, and most circuit board manufacturers have a fixed thickness requirement for the different types of layers they can manufacture, which will greatly limit the number of final stack-up . You may want to work closely with the manufacturer to define the number of stack-up. Impedance control tools should be used to generate target impedance ranges for different layers, taking into account manufacturing tolerances provided by the manufacturer and the effects of adjacent wiring.
In the ideal case of complete signals, all high-speed nodes should be routed in the inner layer of impedance control (such as a stripline). To optimize SI and keep the board decoupled, you should route the ground / power planes in pairs as much as possible. If there can only be one pair of ground / power planes, you are the only one. If there is no power plane at all, you may encounter SI problems by definition. You may also encounter situations where it is difficult to simulate or emulate the performance of the board before the return path of the signal is undefined.
3. Crosstalk and impedance control
Coupling from adjacent signal lines will cause crosstalk and change the impedance of the signal lines. Analysis of the coupling of adjacent parallel signal lines may determine the “safe” or expected spacing (or parallel wiring length) between signal lines or between various types of signal lines. For example, if you want to limit the crosstalk between the clock and the data signal node to less than 100mV, but you need to keep the signal traces parallel, you can find the minimum allowable distance between signals on any given wiring layer through calculation or simulation. At the same time, if the design includes impedance-critical nodes (either clocks or dedicated high-speed memory architectures), you must place the wiring on one (or several) layers to get the desired impedance.